POLSTER Robert 23/9/15Amphithéâtre d entre principal de CEA – Grenoble à 13h.

SUJET : Architecture de liens optiques en photonique silicium (Architecture of silicon photonic links)

Sous la direction de M: Eric Cassan
Son directeur de recherches.
(indiquer les noms par ordre alphabétique)
• Jean-Louis CARBONERO
• Azita Emami
• Jean-Michel FOURNIER
• Remco Stoffer
• Lionel TORRES
• José-Luis Gonzalez-Jimenez (co-encadrant)


Future high performance computer (HPC) systems will face two major challenges: interconnection bandwidth density and power consumption. Silicon photonic technology has been proposed recently as a cost-effective solution to tackle these issues. Currently, copper interconnections are replaced by optical links at rack and board level in HPCs and data centers. The next step is the interconnection of multi-core processors, which are placed in the same package on silicon interposers, and define the basic building blocks of these computers. Several works have demonstrated the possibility of integrating all elements needed for the realization of short optical links on a silicon substrate.

The first contribution of this thesis is the optimization of a silicon photonic link for highest energy efficiency in terms of energy per bit. The optimization provides energy consumption models for the laser, a de- and serialization stage, a ring resonator as modulator and supporting circuitry, a receiver front-end and a decision stage. The optimization shows that the main consumers in optical links is the power consumed by the laser and the modulator's supporting circuitry. Using consumption parameters either gathered by design and simulation or found in recent publications, the optimal bit rate is found in the range between 8 Gbps and 22 Gbps, depending on the used CMOS technology. Nevertheless, if the static power consumption of modulators is reduced it could decrease even below 8 Gbps.

To apply the results from the optimization an optical link receiver was designed and fabricated. It is designed to run at a bit rate of 8 Gbps. The receiver uses time interleaving to reduce the needed clock speed and elevate the need of a dedicated deserialization stage. The front-end was adapted for a wide dynamic input range. In order to take advantage of it, a fast mechanism is proposed to find the optimal threshold voltage to distinguish ones from zeros.

Furthermore, optical clock channels are explored. Using silicon photonics a clock can be distributed to several processors with very low skew. This opens the possibility to clock all chips synchronously, relaxing the requirements for buffers that are needed within the communication channels. The thesis contributes to this research direction by presenting two novel optical clock receivers. Clock distribution inside chips is a major power consumer, with small adaptation the clock receivers could also be used inside on-chip clocking trees.